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12505 tn im / 71003 si im no.7457-1/42 LC89052TA-E 1. overview the LC89052TA-E is an audio lsi that demodulates according to the data format for the data transferred between digital audio devices via the iec 60958/61937 and eiaj cp-1201. it supports sampling frequencies of up to 192khz and output data lengths up to 28 bits. despite it is compact and made in a low cost, the LC89052TA-E includes a built-in oscillator and serial data input circuits and allows the system microcontroller to read th e sub-code q data and channel status. it supports low-power modes that allow low-voltage operation. it also supports a lower power mode, which is suitable for application that requires long battery life, such as cell phones, pdas, and portable audio devices. 2. features ? incorporates a built-in pll circuit to synchron ize with transferred bi -phase mark signal. ? can receive input with sampling fr equencies of 32khz to 192khz. ? can set the upper limit of samp ling frequency of received data. ? can receive input data of specific sampling frequencies. ? outputs the following clocks: fs, 64fs, 128fs, 256fs, 384fs, and 512fs. ? contains a built-in oscillation amplifier that can construct a oscillation circuit. an external clock can be also provided. ? outputs an externally input clock signal that can be us ed as the a/d converter clock when the pll is unlocked. ? maintains the continuity of the output clock when the clock is switched. ? equipped with a serial digital audio data input pin that can be configured for a demodulated signal output. ? can output up to 28 bits of data, and also supports output of i 2 s and input nrz data. ? can output bi-phase mark signal synchronized with the 128fs bit clock. ? provides an output pin for the channel status bit 1 non-pcm data detection bit. ? provides an output pin for the channel status emphasis detection bit. ? supports a lower-power mode. ? calculates the input signal sampling frequency an d outputs it from the microcontroller interface. ? can output the first 48 bits of the channe l status with the micr ocontroller interface. ? can output the 80-bit sub-code q data w ith crc flags via microc ontroller interface. ? outputs various state changes as interrupt signals to the microc ontroller interface. continued on next page. ordering number : enn7457a cmos ic digital audio interface receiver
LC89052TA-E no.7457-2/42 continued from preceding page. ? equipped with a user definable output port that can be selected from the following functions. ?microcontroller interface register output (for power saving mode optical module control signals, etc.) ?signal output of transitional period where vco clock and external input clock are switched. ? can dispense with un-used microcontroller control. ? 3.3v single source power supply (can op erate at a minimum voltage of 2.7v.) ? the ttl input ports can sup port 5v interface operation. ? package: tssop-24 3. package dimensions unit : mm 3260a 4. pin assignments 2 3 4 5 6 7 8 9 10 18 17 16 15 14 13 19 20 ce cl do e / int audio rxin xin sdin lrck bck dgnd a gnd ckout lc89052t a -e nc 11 nc 12 21 22 23 1 24 di ugpi datao xout error pd dv dd top view a v dd lpf
LC89052TA-E no.7457-3/42 5. pin description table 5.1 pin functions pin no. name i/o function 1 xout o oscillation amplifier circuit output pin 2 error o pll lock error and data error output pin 3 ___ pd i 5 system reset and low-power mode control input pin 4 nc non connection 5 ce i 5 microcontroller interface: chip enable input pin 6 cl i 5 microcontroller interface: serial clock input pin 7 di i 5 microcontroller interface: write data input pin 8 do o microcontroller interface: read data output pin 9 e / int o pre-emphasis detection or microcontroller interface interrupt output pin 10 ______ audio o channel status bit 1 non-pcm data detection output pin 11 _____ ugpi o user settable output pin * 12 rxin i 5 digital data input pin 13 dv dd digital power supply pin 14 av dd analog power supply pin 15 lpf o pll loop filter pin 16 nc non connection 17 agnd analog gnd pin 18 dgnd digital gnd pin 19 ckout o system clock output pin ** 20 bck o 64fs clock output pin 21 lrck o fs clock output pin *** 22 datao o demodulated data output pin 23 sdin i 5 serial digital data input pin 24 xin i oscillator or external clock input pin * : microcontroller register output or clock switching transition period signal. ** : 128fs, 256fs, 3 84fs, 512fs, or oscilla tor amplifier outputs. *** : other than i 2 s mode ; low: right channel, high: left channel. i 2 s mode ; low: left channel, high: right channel. 1) i/o voltage handling : i or o pins : ?0.3 to +3.6v, i 5 pins : ?0.3 to +5.5v 2) to prevent logic circuit latch-up, all power supply must be applied or removed simultaneously.
LC89052TA-E no.7457-4/42 6. block diagram pll 9 ckout bck lrck 19 20 21 amp. clock selector demodulation & lock detection audio i/f data buffer fs calu. c & u xout xin 24 1 lpf 15 rxin 12 microcontroller i/f datao 22 error 2 di 7 cl 6 ce 5 pd 3 sdin 23 11 ugpi do 8 e/int audio 10
LC89052TA-E no.7457-5/42 7. electrical characteristics 7.1 absolute maximum ratings table 7.1 absolute maximum ratings at agnd = dgnd = 0v parameter symbol conditions ratings unit maximum supply voltage av dd max 7-1-1 ?0.3 to 4.6 v maximum supply voltage dv dd max 7-1-2 ?0.3 to 4.6 v input voltage 1 v in 1 7-1-3 ?0.3 to 3.9 v input voltage 2 v in 2 7-1-4 ?0.3 to 5.8 v output voltage v out 7-1-5 ?0.3 to 3.9 v storage temperature tstg ?55 to 125 c operating temperature topg ?30 to 70 c maximum output current ii, i out 7-1-6 20 ma 7-1-1 : av dd pin. 7-1-2 : dv dd pin. 7-1-3 : xin pin. 7-1-4 : rxin, sdin, _____ pd, ce, cl, and di pins. 7-1-5 : xout, error, do, e/int, ______ audio, _____ ugpi, ckout, bck, lrck, and datao pins. 7-1-6 : per single input or output pin. 7.2 recommended operating conditions table 7.2 recommended operating conditions parameter symbol conditions min typ max unit supply voltage 1 av dd , dv dd 7-2-1 2.7 3.3 3.6 v supply voltage 2 av dd , dv dd 7-2-2 3.0 3.3 3.6 v input voltage range 1 v in 1 7-2-3 03.3 3.6 v input voltage range 2 v in 2 7-2-4 03.3 5.5 v operating temperature vopg ?30 70 c 7-2-1 : pllck [1:0] = "00" or pllck [1:0] = "01" 7-2-2 : pllck [1:0] = "10" or pllck [1:0] = "11" 7-2-3 : xin pin 7-2-4 : rxin, sdin, _____ pd, ce, cl, and di pins 7.3 input and output pin capacitances table 7.3 input and output pin capacitances parameter symbol conditions min typ max unit input pins c in 7-3-1 10 pf output pins c out 7-3-1 10 pf 7-3-1 : av dd = dv dd = v in 1 = v in 2 = 0 v, ta = 25c, f = 1mhz
LC89052TA-E no.7457-6/42 7.4 dc characteristics table 7.4 dc characteristics at ta = -30 to 70c, av dd = dv dd = 3.0 to 3.6v, agnd = dgnd = 0v parameter symbol conditions min typ max unit high-level input voltage v ih 0.7dv dd v low-level input voltage v il 7-4-1 0.2dv dd v high-level input voltage v ih 2.0 5.8 v low-level input voltage v il 7-4-2 ?0.3 0.8 v high-level output voltage v oh dv dd ? 0.8 v low-level output voltage v ol 7-4-3 0.4 v high-level output voltage v oh dv dd ? 0.8 v low-level output voltage v ol 7-4-4 0.4 v high-level output voltage v oh dv dd ? 0.8 v low-level output voltage v ol 7-4-5 0.4 v power consumption i dd 1 7-4-6 6.5 13 ma power consumption i dd 2 7-4-7 0.1 a power consumption i dd 3 7-4-8 4.5 9 ma power consumption i dd 4 7-4-9 5 10 ma 7-4-1 : cmos level pins: xin pin. 7-4-2 : ttl level pins: input pins other than those listed above. 7-4-3 : i oh = ?8ma, i ol = 6ma: ckout pin. 7-4-4 : i oh = ?2ma, i ol = 2ma: bck, lrck, datao, and do pins. 7-4-5 : i oh = ?1ma, i ol = 1ma: output pins other than those listed above. 7-4-6 : operating mode: pllsel = "0", ampopr = "0", fs = 44.1khz, c l = 30pf 7-4-7 : low power mode condition 1) : ___ pd = low 7-4-8 : low power mode condition 2) : pdown [1:0] = "01", xin = 11.2896mhz, c l = 30pf 7-4-9 : low power mode condition 3) : pdown [1:0] = "10", xin = 11.2896mhz, c l = 30pf
LC89052TA-E no.7457-7/42 7.5 ac characteristics table 7.5 ac characteristics at ta = -30 to 70c, av dd = dv dd = 3.0 to 3.6v, agnd = dgnd = 0v parameter symbol conditions min typ max unit rxin sampling frequency f fs 1 7-5-1 30 195 khz rxin sampling frequency f fs 2 7-5-2 30 108 khz xin clock frequency f xf 1 7-5-3 11.2896 mhz xin clock frequency f xf 2 7-5-4 12.2880 mhz xin clock frequency f xf 3 7-5-5 16.9344 mhz xin clock frequency f xf 4 7-5-6 22.5792 mhz xin clock frequency f xf 5 7-5-7 24.5760 mhz xin clock frequency f xf 6 7-5-8 33.8688 mhz ckout clock frequency f mck 2 100 mhz ckout clock jitter t j 200 ps ckout to bck delay t mbo 10 ns bck to datao delay t bdo 5ns ____ ugpi low-level pulse width t ckt 7-5-9 100 ms 7-5-1 : pllck [1:0] = "00" 7-5-2 : settings other than pllck [1:0] = "00". 7-5-3 : xisel [3:0] = "0000" 7-5-4 : xisel [3:0] = "0001" 7-5-5 : xisel [3:0] = "0010" 7-5-6 : xisel [3:0] = "0100" 7-5-7 : xisel [3:0] = "0101" 7-5-8 : xisel [3:0] = "0110" 7-5-9 : when signal output is set during a transitional period of clock switching. figure 7.1 ac characteristics bc k datao lrc k t bdo ckout t mbo t ckt ugpi
LC89052TA-E no.7457-8/42 7.6 microcontroller interface ac characteristics table 7.6 microcontroller in terface ac characteristics at ta = -30 to 70c, av dd = dv dd = 3.0 to 3.6v, agnd = dgnd = 0v parameter symbol conditions min typ max unit ___ pd low-level pulse width t pddw 200 s e/int high-level pulse width t intuw 7-6-1 5 1/fs 63 s cl low-level pulse width t cldw 100 ns cl high-level pulse width t cluw 100 ns cl to ce setup time t cesetup 50 ns cl to ce hold time t cehold 50 ns cl to di setup time t disetup 50 ns cl to di hold time t dihold 50 ns cl to ce hold time t clhold 50 ns cl to do delay time t cltodo 20 ns ce to do delay time t cetodo 20 ns 7-6-1 : intopf = "1", intsel = "1", and fs is the input sampling frequency. figure 7.2 microcontroller ac characteristics cl di ce do t cldw t cluw t cehold t cesetup t disetup t dihold t cltodo t cetodo t clhold e/int t intud hi-z
LC89052TA-E no.7457-9/42 8. function description 8.1 system reset ( _____ pd) ? the system operates normally when _____ pd pin is set to high level after a supply voltage is rises to 2.7v or higher. when you set the _____ pd pin to low again after power is applied, the system is reset. ? when power is on, resetting must be done with the _____ pd pin set to low. ? if a crystal oscillator is used, you must wait to start normal operation for at least 10ms until the oscillation gets stable after the _____ pd pin goes from low to high. figure 8.1 _____ pd pin levels at power on 8.2 low-power modes ? the LC89052TA-E supports two low-power modes: the mode in which whole circuit is controlled with the _____ pd pin and the mode in which only special functions are controlled by the pdown[1:0]. ? the low-power mode controlled by the _____ pd applies to the entire circuit of th e LC89052TA-E. all clocks are stopped and the registers are initialized. ? the pins that are available with the low-power settings ex cept for the oscillation amplifier are only the xin pin and xout pin. these can be used to provide the master clock for the dsp and other circuits. ? the pins that are available with the pdown[1:0] low-po wer mode settings except those for the oscillator amplifier and its divider circuit are only the ckout, bck, lrck, datao, sdin, xin and xout pins. this mode can be used to minimize power consumption during analog data processing. ? when the oscillator amplifier is stopped by the ampopr in a low-power mode setup with pdown[1:0] or when this circuit is already stopped, it is impossible for the LC89052TA-E to provide a clock output. thus the ampopr takes precedence. note that the pllopr setting is invalid and the pll circuit is stopped. ? when the low-power mode is set with pdown[1:0], it is possi ble to write to the microcontroller registers. however, all the sub-code q and channel status that are read are fixed at a low level. v dd pd 2.7v t 2.0v t > 200
LC89052TA-E no.7457-10/42 ? the table below summaries the low-power modes. table8.1 low-power modes mode ___ pd ampopr pllopr pdown1 pdown0 function (1) low reset (stand-by) (2) 0 0 0 0 normal operation (3) 0 1 0 0 vco stopped. (4) 0 0 1 all circuits except the oscillator amplifier stopped. (5) 0 1 0 all circuits except the oscillator amplifier and divider circuit stopped. (6) 1 0 0 0 oscillator amplifier stopped. (7) high 1 1 all circuits stopped. ? the table below lists the output pin states in the above modes. table 8.2 output pin states in modes (1) to (7) output pin mode (1) mode (2) mode (3 ) mode (4) mode (5) mode (6) mode (7) ______ audio low output low low low output low _____ ugpi high output output output output output output ckout low output output output output output low bck low output output low output output l or h lrck low output output low output output l or h datao low output output low output output low xout high output output output output high high error high output high high high output high e/int low output low low low output low 1) in modes (3), (4), and (5), the clock supplied from the xin pin is used as the source. 2) mode (3) applies to the state where an external clock other than ckout is supplied to xin. if xin pin and ckout pin are connected, no clock signals are output in this mode. 3) mode (6) applies when the pll circuit is locked. when the pll circuit is unlocked, all circuits are stopped since no clock signal is supplied from xin pin. 4) in mode (7), the states immediatly before the setup is retained.
LC89052TA-E no.7457-11/42 8.3 clocks 8.3.1 pll (lpf) ? the LC89052TA-E incorporates a vco (voltage controlled oscillator) that can synchronize with sampling frequencies of 30khz to 195khz. ? the locking frequency is selected with pllck[1:0]. the vco circuit can be stopped with pllopr. ? the range of input data that can be received di ffers depending on the settings of pllck[1:0]. ? the (512/2)fs for the pllck[1:0] = "11" in the table below is the state where the pll itself is synchronized with the 512fs clock, but the clock signal output from the ckout pin is 1/2 of the pll locked frequency, which is 256fs. see the chapter on the of output clock for further information. ? we recommend the 256fs setting with pllck[1:0] = "00" for the systems such as portable equipment that need to restrain the consumption electric power. we also reco mmend the 512fs setting with pllck[1:0] = "10" or the (512/2)fs with pllck[1:0] = "11" for the systems such as av amplifiers that require improved performance. table 8.3 input data reception ranges and pll lock frequency settings pllck1 pllck0 pll lock frequency input data reception range 0 0 256fs 30k to 195khz 0 1 384fs 30k to 108khz 1 0 512fs 30k to 108khz 1 1 (512/2)fs 30k to 108khz ? lpf is the pll loop filter connection pin. use the correct recommended resistance and capacitance as values listed in the table below according to the pllck[1:0] settings. pllck1 pllck0 r0 c0 c1 0 0 0 1 150 ? 0.047 f 0.0068 f 1 0 1 1 150 ? 0.068 f 0.0047 f figure 8.2 pll loop filter configuration lpf r0 c0 c1
LC89052TA-E no.7457-12/42 8.3.2 oscillator amplifier (xin and xout) ? the following methods can be used to supply the clock signal to the intern al oscillator amplifier. figure 8.3 xin and xout pin circuit configurations ? when you connect an oscillator, use the one with the fundamental frequency. since the load capacitance depends on the oscillator characteristics, give careful consideration. ? since the clock supplied to the xin pin is normally used for the following purposes, the clock signal should be present all the time. ?externally supplied clock used when the pll circuit is unlocked and when xin is the clock source ?for calculation of sampling frequencies of the input data ? input a clock with a frequency of 11.2896m, 12.288m, 16.9344m, 22.5792m, 24.576m, or 33.8688mhz according to the setting of the xisel[2:0]. input digital data only after the xisel[2:0] has been set to match the set frequency and the oscillator or external clock input frequency. the LC89052TA-E may malfunction if data is input when the input frequency and the set frequency are not consistent. ? the LC89052TA-E operates even when the frequency set with the xisel[2:0] and the frequency supplied to the xin pin are different. however, continuity at clock switching time and correct input fs calculation are not guaranteed. ? the LC89052TA-E supports a structure in which ckout pin is connected to the xin pin to set xisel3, requiring no oscillator. however, since only vco can be used as the source clock, the vco free-running frequency (10m to 16mhz) is output from the ckout pin when the pll is not locked. furthermore, input fs calculation and limitation are impossible with this approach. also, since no clock is supplied to the oscillator amplifier circuit when the vco is set to stop, the whole system stops. this function is availabl e only for the pllck[1:0] = "00" setting, which is 256fs. other system clock settings might cause malfunction. ? normally the oscillator amplifier stops automatically when the pll is locked. it is possible to change to a continuous operation mode with ampcnt. setting the LC89052TA-E to the continuous operation mode makes it possible to calculate the input sampling frequency even when the pll is locked. however, since both the oscillator amplifier clock and the pll clock signals coexist in that case the user must pay attention and make sure audio quality is not adversely affected. ? the oscillator amplifier can be stopped when not require d by setting the ampopr. however, the application must maintain its state for at least 10ms until the oscillator stabilizes, when returning from stop to operation mode. after that the LC89052TA-E must be returned to the normal operation mode. xin xout ckout xin xout ckout xin xout ckout (a) oscillator element (c) ckout clock signal (b) external clock signal
LC89052TA-E no.7457-13/42 8.3.3 output clocks (ckout, bck, lrck) ? the clock source for the clocks output from ckout, bck, and lrck can be selected from two master clocks, the pll circuit and the xin pin. ? normally, when the pll circuit is locked, the master clock is switched to the pll source, and when the pll circuit is unlocked, the master clock automatically switches to the xin source. to switch the clock source forcibly, set with ocksel. clock continuity is maintained when the clock so urce is selected by the lock ed/unlocked state of the pll circuit or ocksel. ? clock switching depends on the pll circuit locked/unlocked state at the time of the register setup. if the pll source is selected with ocksel when the pll circuit is unlocked , the clock is automatically switched after the pll circuit is locked. ? when vco operation is stopped with pllopr, xin becomes the clock source. however, clock continuity cannot be maintained if the operation is stopped with pllopr while th e pll circuit is locked. when a low-power mode is set, continuity cannot be maintained if the mode is switched from the locked pll. table 8.4 register settings, pll states, and the clock source ocksel 0 1 pll state locked unlocked locked unlocked clock source p ll xin xin xin ? either the pll clock or the xin clock is output from the ckout pin. the divided clock of ckout is output from the bck pin and lrck pin. ? the pll lock time frequency is set with pllck[1:0]. howeve r, it is possible to maintain clock continuity without losing the pll locked state when switching, in the pll lo cked state, from the 512fs setting mode with pllck[1:0] = "10" to the (512/2)fs setting with the pllck[1:0] = "11" , as well as when switching in the reverse direction. ? if you use the following procedure to switch between 512fs and (512/2)fs, the bck and lrck output clock continuity can be maintained, and the ckout output clock frequency can be held within a narrow band. other pllck[1:0] switching would result in a lock error. figure 8.4 flowchart for ckout output clock narrow band operation data input lock detection fs calculation 512fs set pllck0=0 pllck1=1 pllck0=1 pllck1=1 no yes fs=96khz fs=48khz (512/2)fs set ckout output 24.576mhz
LC89052TA-E no.7457-14/42 ? the tables below show the output clocks generated in the xin and pll clock source modes. table 8.5 xin output clocks in clock source mode (xisel2 = "0", pll unlocked state or forced setting) pllck1 pllck0 xisel1 xisel0 ckout pin bck pin lrck pin 0 0 0 0 11.2896mhz 2.8224mhz 44.1khz 0 0 0 1 12.2880mhz 3.0720mhz 48khz 0 0 1 0 16.9344mhz 4.2336mhz 66.15khz 0 1 0 0 11.2896mhz 1.8816mhz 29.4khz 0 1 0 1 12.2880mhz 2.0480mhz 32khz 0 1 1 0 16.9344mhz 2.8224mhz 44.1khz 1 0 0 0 11.2896mhz 2.8224mhz 44.1khz 1 0 0 1 12.2880mhz 3.0720mhz 48khz 1 0 1 0 16.9344mhz 4.2336mhz 66.15khz 1 1 0 0 11.2896mhz 2.8224mhz 44.1khz 1 1 0 1 12.2880mhz 3.0720mhz 48khz 1 1 1 0 16.9344mhz 4.2336mhz 66.15khz table 8.6 xin output clocks in clock source mode (xisel2 = "1", pll unlocked state or forced setting) pllck1 pllck0 xisel1 xisel0 ckout pin bck pin lrck pin 0 0 0 0 22.5792mhz 5.6448mhz 88.2khz 0 0 0 1 24.5760mhz 6.1440mhz 96khz 0 0 1 0 33.8688mhz 8.4672mhz 132.3khz 0 1 0 0 22.5792mhz 3.7632mhz 58.8khz 0 1 0 1 24.5760mhz 4.0960mhz 64khz 0 1 1 0 33.8688mhz 5.6448mhz 88.2khz 1 0 0 0 22.5792mhz 5.6448mhz 88.2khz 1 0 0 1 24.5760mhz 6.1440mhz 96khz 1 0 1 0 33.8688mhz 8.4672mhz 132.3khz 1 1 0 0 22.5792mhz 5.6448mhz 88.2khz 1 1 0 1 24.5760mhz 6.1440mhz 96khz 1 1 1 0 33.8688mhz 8.4672mhz 132.3khz table 8.7 pll output clocks in clock source mode (pll locked state) pllck1 pllck0 ckout pin bck pin lrck pin 0 0 256fs 64fs fs 0 1 384fs 64fs fs 1 0 512fs 64fs fs 1 1 256fs 64fs fs ? the ckout output clock frequency can be set to 1/2 of its normal value with mckhfo, regardless of the pll locked/unlocked state. clock switching with this setting ca n be done without unlocking the pll but clock continuity is not maintained. ? if the audio output format is set to bi-phase data output , the bck output clock frequency is doubled to 128fs when the pll circuit is locked. however, when unlocked, a bck signal shown in the above tables is output. note that the clock continuity is not maintained when this output format is set.
LC89052TA-E no.7457-15/42 8.3.4 clock system diagram ? this section shows the relationship between the two types of master clock and clock switching and dividing functions. ? the items in square brackets near the switch and function blocks are the names of write commands. ? lock/unlock is switched automatically acco rding to the pll lock/unlock state. figure 8.5 master clock system diagram 8.3.5 point to notice when switching the clock source ? if an attempt is made to switch the clock source from pll lock state (oscillator amplifier stopped) to xin using ocksel when a mode in which the results of input fs calculation are reflected in the error flags is specified through flimit, an error signal (h) is temporarily placed at the er ror pin though the continuity of the clock is preserved. the reason for this follows. when the clock switching is carr ied out, the oscillator amplifier is activated and the input fs calculation is restarted. at the same time, the old results of fs calculation are reset and consequently, a change in the fs value is recognized when the old fs value is compared with the newly calculated fs value. ? to switch the clock source using ocksel while maintaining the state of the error pin when the pll is locked in this mode setting, it is necessary to put the oscillator amplifier into the continuous m ode using ampcnt. ? note that when the clock source is switched to xin from th e state where the oscillator amplifier is stopped with the pll circuit locked, output clocks whose source is xin st art outputting after the oscilla tor amplifier has started operation. while the pll is locked, clock source switching from xin to pll is carried out immediately. in both cases, clock continuity is maintained. ? when the ckout clock is supplied to xin without using an oscillator or an external clock, the vco free-running frequency output from the ckout pin with the pll unlocked is somewhere between 10m and 16mhz. clock signals created by dividing ckout are output from bck and lrck pins. however, these clock frequencies vary depending on the LC89052TA-E sample and fluctuate depending on supply voltage and operating environments. therefore, the frequency is not fixed. you need to take care when using the ckout, bck, and lrck clocks while the pll circuit is unlocked. rxin lock/unlock [ocksel] divider 1/2 divider 1/256 ckout bck lrck xin xout pll (256fs) [pllck0] [xisel0] (384fs) [pllopr] [ampcnt] 1/3 1/384 [xinset] [ampopr] [xisel1] [pllck1] [xisel2] (512fs) 1/512 (512/2fs) divider 1/2 [mckhfo] 1/4 1/6 1/8
LC89052TA-E no.7457-16/42 8.4 data input and output 8.4.1 bi-phase mark modulated digital data input (rxin) ? rxin is an input pin for bi-phase mark modulated digital data. ? the rxin pin supports ttl levels. this allows a 5v -optical reception module to be connected directly. 8.4.2 setting the bi-phase mark m odulated input data reception range ? the LC89052TA-E allows the user to set the upper limit sampling frequency of the receivable input data and can receive input data of specific sampling frequencies. ? these are set with flimit and fssel[3:0]. ? however, this function does not work in modes wher e the reception range is not limited with the flimit. table 8.8 input data reception range (fs4xin = "0") fssel3 fssel2 fssel1 fssel0 input data reception range 0 0 0 0 32khz to 96khz 0 0 0 1 32khz only 0 0 1 0 44.1khz only 0 0 1 1 48khz only 0 1 0 0 88.2khz only 0 1 0 1 96khz only 0 1 1 0 44.1khz or 88.2khz only 0 1 1 1 48khz or 96khz only 1 0 0 0 32khz or 44.1khz or 48khz 1 ?. 1 0 ?.. 1 0 ?.. 1 1 ?.. 1 reserved ? the notation 32khz to 96khz means 32k, 44.1k, 48k, 64k, 88.2k, or 96khz. ? the table above only applies when the input fs calculation mode (fs4xin) is set to "0". when fs4xin is set to "1", input data reception range is doubled. ? input data out of the set range is treated as an error, in which case the xin source clock is output. at this time, the datao output data is subject to the rdtsel setting. ? when the pll follows a source with a variable fs, such as a cd player with variable p itch control, from the state where the oscillator amplifier is stopped while pll is locked, the fs is not calculated. as a result, an input frequency not within the set range is not regarded as an error. th e oscillator amplifier must be set to a continuous operation mode to support such sources. ? the reception range of input data can not be limited when setting up a system where no oscillator is required as xin and ckout are connected, because fs cal culation is impossible in that case.
LC89052TA-E no.7457-17/42 8.4.3 output data formats: normal mode (datao) ? the output format of after-demodulation audio data must be set with ofsel[2:0]. ? in the format shown below, the input data only within the audio data range is output. ? bck, lrck, and datao are output in synchronization with the rising edge of ckout. datao is output in synchronization with the falling edge of bck. ? generation of output data starts at the lrck edge immediately after the error output turns low. ? the low level is output all the time except for the effective bit length of output data. figure 8.6 data output timing (normal mode) lrc k bc k datao lrc k bc k datao lrc k bc k datao lsb msb 16, 20, 24 bits 16, 20, 24 bits l-ch r-ch lsb msb lsb msb l-ch r-ch lsb msb 16 to 24 bits 16 to 24 bits 16 to 24 bits 16 to 24 bits lsb msb l-ch r-ch lsb msb (0) : msb first left-justified data output (ofsel[2 : 0]=000) (1) : i 2 s data output (ofsel[2 : 0]=001) (2) : msb first right-justified data output (ofsel[2 : 0]=010, 011 or 100)
LC89052TA-E no.7457-18/42 8.4.4 output data formats: special mode (datao) ? the output format of after-demodulation audio data must be set with ofsel[2:0]. ? in the format shown below, input data information except the audio data is output as well. ? bck, lrck, and datao are output in synchronization with the rising edge of ckout. datao is output in synchronization with the falling edge of bck. ? generation of output data starts at the lrck edge immediately after the error output turns low. ? (3) as bi-phase data output, the input bi-phase data is output in synchronization with 128fs clock bck and fs clock lrck. however, bck in pll unlocked state is set to the 64fs clock. ? as for nrz data output in (4), (5), 28bits are output. 4 bits of validity (v), user data (u), channel status (c) and also preamble b (z) plus 24 bits of lsb first audio data. h is output as z bit in the frames (l-ch and r-ch) whose preamble b is confirmed. ? the low level is output all the time except for the effective bit length of the nrz data output. figure 8.7 data output timing (special mode) (3) : biphase data output (ofsel[2 : 0]=101) lrc k bc k datao lrc k bc k datao lrc k bc k datao lsb 28 bits l-ch r-ch lsb msb lsb 28 bits l-ch r-ch vz notice : "z" means preamble "b" -24 bit- lsb l-ch r-ch 28 bits 28 bits c lsb v p u c msb v p u c uc msb lsb v z -24 bit- u c msb v z -24 bit- u c msb v z -24 bit- u c notice : "z" means preamble "b" (4) : nrz data i 2 s output (ofsel[2 : 0]=110) (5) : nrz data lsb first left-justified output (ofsel[2 : 0]=111) p msb
LC89052TA-E no.7457-19/42 8.4.5 serial audio data input format (sdin) ? sdin is the pin that inputs serial digital audio data such as a/d converter output. ? data input to the sdin can be output from the datao pin. the data to be input to sdin must synchronize with bck and lrck. ? given below shows an example of a serial audio data input timing. ? except for a special setting, we suggest the sdin input form at be consistent with the format of output data after demodulation. figure 8.8 example of serial audio data input timing (0) : msb first left-justified data input lrc k bc k sdin lrc k bc k sdin lrc k bc k sdin lsb msb l-ch r-ch lsb msb lsb msb l-ch r-ch lsb msb lsb msb l-ch r-ch lsb msb 16, 20, 24 bits 16, 20, 24 bits 16 to 24 bits 16 to 24 bits 16 to 24 bits 16 to 24 bits (1) : i 2 s data input (2) : msb first right-justified data input
LC89052TA-E no.7457-20/42 8.4.6 output data swit ching (sdin, datao) ? the datao pin outputs the demodulated data when the pll circuit is locked and the sdin input data when the pll circuit is unlocked. this switching is performed automatically according to the locked/unl ocked state of the pll circuit. ? the data input to sdin must be synchronized with ckout, bck, and lrck clocks when xin is the clock source. ? the sdin input data is output to da tao by setting rdtsta, regardless of the pll circuit locked/unlocked state. in this case, the ckout, bck, and lrck clocks are also switched to the xin clock source. the switch occurs in synchronization with the lrck edge after rdtsta setup. ? the datao output data can also be forcibly muted by setting rdtmut. the muting processing is output in synchronization with the lrck edge after rdtmut setup. ? the datao output can also be muted in the pll unlocked state by rdtsel setup. ? these setups take priority in the follo wing order: rdtsel < rdtsta < rdtmut. ? when xin is set to be the clock source with ocksel, the pll circuit operates as long as pll operation is not stopped with pdown[1:0] or pllopr. in this mode the state of the pll circuit is always output from the error pin. information processed regardless of the pll state can be read out over the microcontroller interface. figure 8.9 timing chart for datao output data switching (when rdtsel is set to "0") 8.4.7 calculation of input data sampling frequency ? the input data sampling frequency is calculated using the xin clock. ? normally, in modes where the oscillator amplifier is automatically stopped when the pll circuit is locked, the calculation is done during the error period associated with error and completed, and the value is retained when the oscillator amplifier is stopped. therefor e, after the calculation is confirmed, the value does not change until the pll circuit is unlocked. ? in continuous operation mode, the oscillator amplifier continuously repeats calculations. ? the calculation result can be read out from ccb address 0xec or output registers do4 to do6. however, note that while the pll can synchronize with data of 32k to 192khz, fs calculation mode can be selected from two modes: 32k to 96khz calculation mode and 64k to 192khz calculation mode. these modes are switched by fs4xin. it is not possible to monitor the fs calculation result of 32k to 192khz in the same mode. ? if a system where the xin and ckout pins are connected an d no oscillator is required is being setup, the fs calculation result will always be "out of range". error ugpi datao unlock lock unlock ugpi : when the clock switching transition period signal is selected pll locked state sdin data muted demodulated data muted sdin data
LC89052TA-E no.7457-21/42 8.5 error output processing (error) 8.5.1 lock error and data error output ? the error pin outputs high level when a pll lock error happens or an error occurs in the transmitted data. 8.5.2 pll lock error ? the pll circuit will unlock the input data which does not conform to the bi-phase modulation rules or can not detect the preamble b, m, or w. ? error turns to h when a pll lock error occurs. when data modulation returns to the normal state, it remains high for 15m to 50ms, before going to the to low level. ? the output of error is synchronized with lrck. 8.5.3 input data transmission error ? an odd number of input parity errors are det ected from the parity bits in the input data. ? when input parity errors occur 9 times or more in a row, e rror turns to high level. after the high level is held for 15m to 50ms following the detection of the pll lock state, the error returns to low level. ? when 8 or fewer input parity errors occur consecutively, an error is output only for intervals between sub-frames where the errors occurred when non-pcm data is recognized by data delimiter bit 1 in the channel status. in this case, the parity error flag is not output when pcm data is recognized. 8.5.4 other errors ? even when error has turned to low, the LC89052TA-E always acquires bits 24 to 27 (sampling frequency) of the channel status and compares the curren t data with the data of the previous block. if any differences are found, error is immediately set to high and processes simi lar to those for the pll lock error are carried out. ? similarly, even when the mode that refl ects fs calculation results in an error flag is set with flimit, the fs calculation results are always compared. here as well, if a disparity occurs in the data, error is immediately turned to high, and the processing similar to that fo r the pll lock error is carried out.
LC89052TA-E no.7457-22/42 8.5.5 data processing upon occurrence of errors ? this section describes the data processing performed when an error occurs. when up to 8 consecutive input parity errors occur, if the transmitted data is pcm audio data, th e data is replaced with the corresponding left and right channel data from the immediately precedin g frame. however, if the transmitted da ta is non-pcm data, the error data is output as it is. non-pcm data is based on the data that is detected before the input par ity error has occurred, and is the data for which the channel status bit 1 non-pcm data detection bit is "1". non-pcm data refers to the data established when bit 1 non-pcm data detection bit of the channel status turns to high based on the data detected prior to the occurrence of the input parity error. ? the output data when a pll lock error or 9 or mo re parity errors occur consecutively are muted. ? for the channel status data, the data for the previous block held in 1 bit units is output when an 8 or less parity error occurs successively. table 8.9 data processing when errors occur data and detection flags pll lock error input parity error (a) input parity error (b) input parity error (c) datao output pin low low previous data output input fs calculation low low output output channel status data low low previous data previous data sub-code q data low low output ? 1) input parity error (a): when 9 or more consecutive parity errors occur 2) input parity error (b): when up to 8 consecutive parity errors occur in audio data 3) input parity error (c): when up to 8 consecutive parity errors occur in non-pcm burst data ? the figure below presents an example of the data processing performed when a parity error occurs. figure 8.10 data processing example for a parity error (when pcm data is received) r-ch previous data value error lrck datao l-1 r-1 l-2 r-2 l-3 r-3 l-4 r-4 l-1 l-2 r-2 l-0 r-0 l-5 r-5 l-6 r-6 l-ch r-ch .... previous data value r-0 l-2 r-2 l-2 l-7 r-7 l-8 r-8 r-2 l-2 r-2 l-2 r-2 input data an error occurs muted after 9 or more consecutive errors
LC89052TA-E no.7457-23/42 8.5.6 processing during error recovery ? when the preambles b, m, and w are detected, the pll circ uit goes to the locked state and data demodulation starts. ? the datao output data is output on the first lrck edge after error goes low. figure 8.11 data processing when data demodulation starts 8.6 channel status data output 8.6.1 data delimiter bit 1 output ( ______________ audio ) ? ______________ audio outputs channel status bit 1, which indicates whether or not the input bi-phase data is pcm audio data. table 8.10 ______________ audio output ______ audio pin output conditions low pcm audio data (cs bit 1 = low) high non-pcm data (cs bit 1 = high) 8.6.2 emphasis information output (e/int) ? e/int is shared by the microcontro ller interface interrupt function. howeve r, in the initial state, it outputs the presence or absence of emphasis with a time constant of 50/15 s for use in consumer products or broadcast studios. table 8.11 e/int output e/int pin output conditions low no pre-emphasis high 50/15s pre-emphasis error datao lrc k output starts at the lrck edge immediately following the fall of the error flag. 15 ms to 50 ms ok internal clock signal data
LC89052TA-E no.7457-24/42 8.7 user general definable output port ( __________ ugpi ) ? __________ ugpi pin is a user-definable output port that can be selected for the following functions. ?microcontroller interface register output ?signal output during clock switching transitional period ? selection is done by gpisel . the initial setting is set to the micr ocontroller interface register gpidat . however, the initial setting of this gpidat register is "1", so high level is output from the __________ ugpi pin. 8.7.1 microcontroller interface regist er output (example of signals that control low power of optical module) ? this section describes an example in which __________ ugpi is used as a power supply control signal for an optical module as a microcontroller interf ace register output. (a) connect the __________ ugpi output to the power supply control switch of the optical module. (b) after a reset due to _____ pd, microcontroller interface register output is selected as the initial state of __________ ugpi . as a result, the default gpidat value is output. (c) after a reset, the initial value of gpidat is set to "1", so h is output from __________ ugpi . therefore, after a reset, the control switch is turned off, and data is not supplied from the optical module. (d) the application must set gpidat to "0" to have the optical module supply data. that is, the __________ ugpi output can be controlled with gpidat, and the current drain can be minimized when the optical module is not used. figure 8.12 __________ ugpi output example (power supply control signal for an optical module) LC89052TA-E ugpi rxin optical receiver module
LC89052TA-E no.7457-25/42 8.7.2 microcontroller interface register output (example of signals that cont rol switching of digital data input) ? __________ ugpi , when used as a microcontroller interface register output , can be used as a control signal that switches the digital data input. ? when increasing the number of digital data input systems, an peripheral circuit such as an input selector and a control signal for that selector is required. the number of digital data input ports can be increased to two systems without having to provide a control signal from the microcontroller by using the __________ ugpi output. ? note that after a reset, the initial value of gpid at is set to "1", so high level is output from __________ ugpi . be aware that the initial value of the switching signal is high level. figure 8.13 __________ ugpi output example (signal that controls the switching of data input) LC89052TA-E ugpi rxin sw
LC89052TA-E no.7457-26/42 8.7.3 output of clock switch transition signal ? this section describes the operation when __________ ugpi is selected as an output pin during the clock switching transitional period. ? a clock switching transitional period signal is a signal that reports a clock switching condition to external circuits due to a change in the pll locked/unlocked state. this sign al allows the application to grasp the pll lock state transitions and the timing of change in the clock signals. this setup is selected with gpisel. ? after setting gpisel, high level is output from __________ ugpi . low pulse is output when the output clock changes due to the change in the pll circu it locked/unlocked state. ? in the lock in process, the __________ ugpi low pulse rises with the word clock generated by the xin clock after input data is detected and pll is locked. after a certain period, it rises with the same timing as error. ? in the unlock process, the __________ ugpi low pulse falls at the same timing as error, which is the pll lock detecting signal and it rises after the word clocks generated from the xin clock are counted for a certain period. figure 8.14 clock switching timing vco cloc k xtal cloc k ckout (a) : during the lock-in process ugpi error pll lock state unlocked locked locked unlocked (b) : during the unlock process rxin digital data digital data after pll lock with the same timing as error 64/fs (s) 15 ms to 50 ms vco cloc k xtal cloc k ckout ugpi error pll lock state rxin with the same timing as error
LC89052TA-E no.7457-27/42 9 microcontroller interface (e/int, ce, cl, di, do) 9.1 interrupt output (e/int) ? the e/int pin can be set to function as the microcon troller interface interrupt output by setting intsel. ? an interrupt output is issued when a change occurs in the pll lock state or output data information. ? the interrupt output consists of registers for selecting interrupts, the e/int pin, which outputs those state transitions, and registers that store interrupt related data. ? the e/int pin normally is at the low level, and goes to the high level when an interrupt occurs. after going to high level, it returns to low level according to the intopf setting. ? intopf determines whether the e/int pin holds the high puls e for a certain period and is then cleared (returning to low), or the e/int pin is cleared at the sa me time as the output register is read. ? the interrupts can be selected from the so urces listed below. more than one items can be set as interrupt sources at the same time by setting the contents of ccb address 0xea. the interrupt signal is issued whenever any one of the interrupt sources arises. e/int output = (selected interrupt 1) + (selecte d interrupt 2) + ... + (selected interrupt n) table 9.1 interrupt source settings no. command description 1 interr output when the state of the error pin changes. 2 intpcm output when the state of the ______ audio pin changes. 3 intemp output when the state of the pre-emphasis information changes. 4 intvfl output when the state of the validity flag changes. 5 intfsc output when the input fs calculation result changes. 6 intcsf output when the first 48 bits of the channel status data are updated. 7 intsqy output when the sub-code q data can be read out. ? the contents of the set interrupt source are stored in ou tput registers do1 to do7 at ccb address 0xeb when an interrupt source arises. however, the registers read for source items 1 through 4 output the current state of those sources regardless of the e/int output. for source items 5 thro ugh 7, the states are stored when an interrupt source arises. ? to monitor interrupt source item 5 in the pll locked state, the oscillator amplifier must be set to continuous operation mode, since the oscillator amplifier clock is used. ? when the LC89052TA-E is set to the mode in which a h pu lse is output from e/int when an interrupt source occurs, the pulse width of each interrupt source is somewhere between 1/2 fs and 3/2 fs. ? the action to clear the e/int pin output simultaneously with the reading of the output registers following the occurrence of an interrupt is carried ou t immediately after the output registers at 0xeb are set up. since, however, the data associated with interrupt sources 6 and 7 is updated at the intervals listed below, it must be read promptly whenever the corresponding in terrupt sources are detected. table 9.2 data update intervals (input fs = 32k to 96khz) data update interval channel status and preamble b 2ms to 6ms sub-code q data 13.3ms (fs = 44.1khz), 6.65ms (2x speed)
LC89052TA-E no.7457-28/42 9.2 ccb addresses ? setting various functions, and reading and writing data must be carried out though th e microcontroller interface. ? the data through the microcontroller inte rface conforms to the sanyo?s original serial bus format (ccb). however, the three-state is employed instead of open-drain as the data output type. ? data must be input or output after the ccb address is input. see the i/o timing chart for details of the data input and output timing. table 9.3 register i/o content and ccb addresses register content r/w ccb address b0 b1 b2 b3 a0 a1 a2 a3 function settings data 1 write 0xe8 0 0 0 1 0 1 1 1 function settings data 2 write 0xe9 1 0 0 1 0 1 1 1 function settings data 3 write 0xea 0 1 0 1 0 1 1 1 interrupt data output read 0xeb 1 1 0 1 0 1 1 1 fs value, cs data output read 0xec 0 0 1 1 0 1 1 1 sub-code q data output read 0xed 1 0 1 1 0 1 1 1 9.3 data write procedure ? the bit length of data input is 16 bits. ? after inputting one of the ccb addresses data 0x e8 to 0xea, set ce to the high level. ? input data is taken in on the rising edge of cl. ? the bits marked "0" in the table are reserved bits. 0 (zero) must be input to these bits. 9.4 data read procedure ? read data is output from do. do goes to the high-impedance state when ce is low, and output starts on the ce rising edge that follows the output setup with the ccb address. after that, the do pin is re turned to the high-impedance state when ce is set low. ? the number of data bits read differs with the data to be re ad. interrupt data (0xeb) is 8 bits long, the channel status related data (0xec) is 56 bits long, and the sub-code q data (0xed) is 88 bits long. however, it is not necessary to read out all data bits. during readout, an application can stop providing cl input and set ce low and still have acquired the data read up to that point. for example, when reading the sub-code q data, if the crc flags are read and the data is found no good, there is no need to read the subsequent data.
LC89052TA-E no.7457-29/42 9.5 input/output timing figure 9.1 input timing chart (normal low clock) figure 9.2 input timing chart (normal high clock) figure 9.3 output timing chart (normal low clock) figure 9.4 output timing chart (normal high clock. it is necessary to read do0 with a port.) ? in the output timing shown in figure 9.4, data is allocated so that there are no problems even if the output register do0 is not read. see the read register table for details. cl b0 b1 b2 b3 a 0 a 1 a 2 a 3 di0 di1 di2 di5 di15 ce di do . . . . di3 di4 hi-z cl b0 b1 b2 b3 a 0 a 1 a 2 a 3 di1 di2 di5 di15 ce di do di0 . . . . di3 di4 hi-z cl b0 b1 b2 b3 a 0 a 1 a 2 a 3 ce di do do0 do1 do2 do3 do4 . . . . don hi-z cl b0 b1 b2 b3 a 0 a 1 a 2 a 3 ce di do hi-z . . . . do1 do2 do3 do4 . . . . don . . . . . . . . do0
LC89052TA-E no.7457-30/42 9.6 write registers 9.6.1 list of write registers ? the table shows the write registers. table 9.4 write register map input register 0xe8 0xe9 0xea di0 sysrst gpisel intopf di1 0 gpidat 0 di2 pdown0 flimit 0 di3 pdown1 fs4xin 0 di4 pllopr fssel0 0 di5 pllck0 fssel1 0 di6 pllck1 fssel2 0 di7 mckhfo fssel3 0 di8 0 ofsel0 intsel di9 ampopr ofsel1 interr di10 ampcnt ofsel2 intpcm di11 ocksel 0 intemp di12 xisel0 rdtsel intvfl di13 xisel1 rdtsta intfsc di14 xisel2 rdtmut intcsf di15 xisel3 0 intsqy ? the shaded columns indicate reserved bits. input 0 (zero) to these bits.
LC89052TA-E no.7457-31/42 9.6.2 details of write data table 9.5 input register function settings 1: system settings (0xe8) di7 di6 di5 di4 di3 di2 di1 di0 mckhfo pllck1 pllck0 pllopr pdown1 pdown0 0 sysrst di15 di14 di13 di12 di11 di10 di9 di8 xisel3 xisel2 xisel1 xisel0 ocksel ampcnt ampopr 0 sysrst: system reset 0: no reset performed (initial value) 1: reset all circuits other than the command registers. pdown[1:0]: low power mode settings (only specific functions are enabled.) 00: normal operation (initial value) 01: only the oscillator amplifier is enabled. 10: only the oscillator amplifier and the output clock divider are enabled. 11: reserved pllopr: pll (vco) operate/stop setting 0: operate (initial value) 1: stop pllck[1:0]: clock frequency setting in the pll locked state 00: 256fs (initial value) 01: 384fs 10: 512fs 11: (512/2)fs = 256fs mckhfo: frequency setting of ckout output clock 0: 1/1 output (initial value) 1: 1/2 output ? it is possible to maintain clock continuity when switchi ng from the 512fs setting with pllck[1:0] = "10" to the (512/2) fs setting with pllck[1:0] = "11", and switching vice versa without entering the pll lock error state. ? for systems that must minimize power consumption such as portable equipment, we recommend the pllck[1:0] = "00" (256fs) setting. for systems that require improved performance such as av am plifiers, we recommend the pllck[1:0] = "10" (512fs) or pllc k[1:0] = "11" (512/2fs) setting.
LC89052TA-E no.7457-32/42 ampopr: oscillator amplifier operate / stop setting 0: operate (initial value) 1: stop ampcnt: oscillator amplifier state setting 0: automatically stop in the pll locked state (initial value) 1: always operate continuously ocksel: clock source setting 0: use the xin clock as the source when the pll is unlocked. (initial value) 1: use the xin clock as the source regardless of the pll state. xisel[3:0]: xin input frequency setting 0000: 11.2896mhz (initial value) 0001: 12.288mhz 0010: 16.9344mhz 0011: reserved 0001: 22.5792mhz 0010: 24.576mhz 0010: 33.8688mhz 0011: reserved 1xxx: must be set when the ck out pin and the xin pin are connected.
LC89052TA-E no.7457-33/42 table 9.6 input register function settings 1: i/o data settings (0xe9) di7 di6 di5 di4 di3 di2 di1 di0 fssel3 fssel2 fssel1 fssel0 fs4x in flimit gpidat gpisel di15 di14 di13 di12 di11 di10 di9 di8 0 rdtmut rdtsta rdtsel 0 ofsel2 ofsel1 ofsel1 gpisel: __________ ugpi pin setting 0: outputs the microcontroller in terface register state. (initial value) 1: outputs clock switching transitional period signal. gpidat: __________ ugpi output setting (valid only when register output mode is set.) 0: outputs the low level. 1: outputs the high level. (initial value) flimit: input data reception limit setting 0: reception is not limited. all data within the pll locked range can be received. (initial value) 1: reception is limited. the input fs calcu lation result is reflected in the error flag according to the fssel[3:0] setting. fs4xin: input fs calculation range setting 0: perform fs calculation for input data in the range of 32k to 96 khz. (initial value) 1: perform fs calculation for input data in the range of 64k to 192 khz. fssel[3:0]: input data reception range set ting (when flimit = "1" and fs4xin = "0") 0000: 32k, 44.1k, 48k, 64k, 88.2k, or 96khz (initial value) 0001: 32khz only 0010: 44.1khz only 0011: 48khz 0100: 88.2khz only 0101: 96khz only 0110: 44.1k or 88.2khz only 0111: 48k or 96khz only 1000: 32k or 44.1k or 48khz 1001-1111:reserved
LC89052TA-E no.7457-34/42 fssel[3:0]: input data reception range set ting (when flimit = "1" and fs4xin = "1") 0000: 64k, 88.2k, 96k 128k, 176.4k, or 192khz (initial value) 0001: 64khz only 0010: 88.2khz only 0011: 96khz only 0100: 176.4khz only 0101: 192khz only 0110: 88.2k or 176.4khz only 0111: 96k or 192khz only 1000: 64k or 88.2k or 96khz only 1001-1111: reserved ofsel[2:0]: serial audio data output format setting 000: 24-bit msb first left-justified data output (initial value) 001: 24-bit i 2 s data output 010: 24-bit msb first right-justified data output 011: 20-bit msb first right-justified data output 100: 16-bit msb first right-justified data output 101-100: reserved 101: bi-phase data output 110: 28-bit i 2 s data output (nrz data output) 111: 28-bit lsb first left-justified data output (nrz data output) rdtsel: pll unlocked state datao output setting 0: output the sdin data in th e pll unlocked state. (initial value) 1: mute the output in the pll unlocked state. rdtsta: datao output setting 0: follow the rdtsel setting. (initial value) 1: output the sdin data regardless of the pll state. rdtmut: datao mute setting 0: output the data selected by rdtsel. (initial value) 1: mute the output.
LC89052TA-E no.7457-35/42 table 9.7 input register function settings 1: interrupt settings (0xea) di7 di6 di5 di4 di3 di2 di1 di0 0 0 0 0 0 0 0 intopf di15 di14 di13 di12 di11 di10 di9 di8 intqsy intcsf intfsc intvfl intemp intpcm interr intsel intopf: e/int output setting (v alid only when the interrupt output function is selected.) 0: output a high level when an interrupt occurs. (initial value) 1: output a high-level pu lse when an interrupt occurs. ? when e/int is set up with intopf for going to the high leve l when an interrupt is generated, the high level state is maintained until the interrupt source output (address 0xeb) is read out. when that data is read, the e/int output returns to the normal low level.
LC89052TA-E no.7457-36/42 intsel: e/int pin setting 0: output emphasis information of the channel status. (initial value) 1: output the interrupt sign al for the microcontroller interface. interr: error signal output setting 0: do not output this signal. (initial value) 1: output the change in the error pin state. intpcm: ______________ audio signal output setting 0: do not output this signal. (initial value) 1: output the change in the ______________ audio pin state. intemp: setting of emphasis detection flag output of channel status 0: do not output this flag. (initial value) 1: output the emphasis detection flag. intvfl: setting of validity flag detection flag output 0: do not output this flag. (initial value) 1: output the validity flag. intfsc: setting of updated flag output of pll lock frequency calculation result 0: do not output this flag. (initial value) 1: output updated flag for the pll lock frequency calculation result. intcsf: setting of updated flag output of the first 48 bits channel status data 0: do not output this flag. (initial value) 1: output the updated flag for the first 48 bits of channel status data. intqsy: setting of signal detection flag output of sub-code q data readout load 0: do not output this flag. (initial value) 1: output the updated flag for the 80 bits of sub-code q data including the crc. ? use intfsc, the updated flag, of pll lock frequency calcula tion result together with interr that output the change in the error state. intfsc is compared with the target fs of the input fs calculation result. when an fs change other than the target fs is found and the fs change doesn? t contain a pll lock error, in tfsc is valid and the updated flag is output. however, if the fs change contains a pll lo ck error, then intfsc is not valid as a lock error process occurs first and the updated flag is not output. ? the channel status updated flag is computed by comparing the current data with the first 48 bits of the previous block. if those data are identical, the channel stat us is updated and the flag is output.
LC89052TA-E no.7457-37/42 9.7 read registers 9.7.1 list of read registers ? the table shows the read registers. table 9.8 read register map output register 0xeb 0xec 0xed do0 0 0 crc do1 outerr outerr crc do2 outpcm outpcm 0 do3 outemp 0 0 do4 outvfl fscal0 0 do5 outfsc fscal1 0 do6 outcsf fscal2 0 do7 outsqy 0 0 do8 0 bit 0 control do9 0 bit 1 control do10 0 bit 2 control do11 0 bit 3 control do12 0 bit 4 address do13 0 bit 5 address do14 0 bit 6 address do15 0 bit 7 address do16 0 bit 8 track do17 0 bit 9 track do18 0 bit 10 track do19 0 bit 11 track do20 0 bit 12 track do21 0 bit 13 track do22 0 bit 14 track do23 0 bit 15 track do24 0 bit 16 index ?.. 0 ?.. ?.. do54 0 bit 46 frame do55 0 bit 47 frame do56 0 0 zero ?.. 0 0 ?.. do86 0 0 abs frame do87 0 0 abs frame ? d00 and d01 (crc) at chip address 0xed are loaded with the same value.
LC89052TA-E no.7457-38/42 9.7.2 details of read data table 9.9 output register: interrupt data output (0xeb) do7 do6 do5 do4 do3 do2 do1 do0 outsqy outcsf outfsc outvfl outemp outpcm outerr 0 outerr: error output (outputs the read-time state.) 0: no transmission er ror in the pll locked state 1: either a transmission error occurred or the pll circuit is in the unlocked state. outpcm: ______________ audio output (outputs the read-time state.) 0: non-pcm signal not detected. 1: non-pcm signal detected. outemp: channel status emphasis dete ction (outputs the read-time state.) 0: no pre-emphasis. 1: 50/15s pre-emphasis. outvfl: validity flag detection (outputs the read-time state.) 0: no error. 1: error detected. outfsc: updated result of input fs calculation (cleared after read.) 0: input fs calculation result not updated. 1: input fs calculation result updated. outcsf: updated result of first 48 bits of channel status (cleared after read.) 0: not updated. 1: updated. outqsy: detection of sub-code q data readout load signal (cleared after read.) 0: not detected. 1: detected.
LC89052TA-E no.7457-39/42 table 9.10 output register: input fs calculation result and channel status data (0xec) do7 do6 do5 do4 do3 do2 do1 do0 0 0 fscal2 fscal1 fscal0 0 outpcm outerr 0 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 32 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 40 bit 39 bit 38 bit 37 bit 36 bit 35 bit 34 bit 33 bit 32 48 bit 47 bit 46 bit 45 bit 44 bit 43 bit 42 bit 41 bit 40 ? the error information, non-pcm informatio n, input fs calculation result, and channel status data can be read from this register. note that the error inform ation and the non-pcm data information are identical to those at 0xeb. outerr: error output (outputs the read-time state.) 0: no transmission er ror in the pll locked state 1: either a transmission error occurred or the pll circuit is in the unlocked state. outpcm: ____________ audio output (outputs the read-time state.) 0: non-pcm signal not detected. 1: non-pcm signal detected. ? the input data fs calculation results are allocated as follow s. the target calculation frequency differs depending on the fs4xin setting. the calculation range also differs slightly depending on the xin clock frequency. table 9.11 input fs calculation result (ta = 25c, v dd = 3.3v, xin = 11.2896mhz) fs4xin = 0 fs4xin = 1 fscal2 fscal1 fscal0 target fs calculated range target fs calculated range 0 0 0 out of range ? out of range ? 0 0 1 32khz 30.9k to 33.2khz 64khz 62.0k to 66.4khz 0 1 0 44.1khz 42.5k to 45.8khz 88.2khz 85.5k to 91.0khz 0 1 1 48khz 46.3k to 49.9khz 96khz 92.6k to 99.0khz 1 0 0 64khz 62.1k to 66.4khz 128khz 124.0k to 132.8khz 1 0 1 88.2khz 85.6k to 91.0khz 176.4khz 171.0k to 182.2khz 1 1 0 96khz 92.6k to 99.0khz 192khz 185.1k to 198.0khz 1 1 1 ? ? ? ? ? the first 48 bits of channel status can be read. ? since the channel status consists of 192 frames, updated data can always be read by reading at the interval 192 times the period of the input sampling frequency. ? it is also possible to read by using the updated flag of the interrupt source and setting e/int to interrupt output to reduce the load of the microcontroller. this flag is output wh en the first 48 bits of the current data is compared with the data of the previous block and found that those data are identical.
LC89052TA-E no.7457-40/42 table 9.12 output register: sub-code q data with crc flag (0xed) do7 do6 do5 do4 do3 do2 do1 do0 0 0 0 0 0 0 0 crc crc 8 address address addres s address control cont rol control control 16 track track track track track track track track 24 index index index index index index index index 32 minute minute minute minute minute minute minute minute 40 second second second second second second second second 48 frame frame frame frame frame frame frame frame 56 zero zero zero zero zero zero zero zero 64 abs minute abs minute abs minute abs minute abs minute abs minute abs minute abs minute 72 abs second abs second abs sec ond abs second abs second abs second abs second abs second 80 abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame ? when sub-code q data is included in the input data, this data can be read together with the crc calculation result. ? to read the sub-code q data, e/int must be set to be selected as an interrupt output so that the sub-code q data readout load signal can be output. ? when sub-code q data is detected, the e/int signal outputs a high level or a high-level pulse. the sub-code q data is updated on each rising edge of the e/int signal. the read out must be completed within 13.3ms (standard speed) or 6.6ms (2 speed), starting at the e/int rising edge. ? the cyclic redundancy code (crc) is a set of flags that deci de whether the 80 bits of sub-code q data is correct. note that the same data is loaded into both the do0 and do1 crc flags. table 9.13 crc flag output crc output conditions low errors are found in the sub-code q data. high the sub-code q data is correct.
LC89052TA-E no.7457-41/42 10 application example ? decoupling capacitors (0.1 f) for the power supply pin, should be locat ed as close to the LC89052TA-E as possible. use ceramic capacitors with good high frequency characteristics as the decoup ling capacitors. use a capacitor with a minimal thermal coefficient for the pll loop filter capacitor. ? there are no constraints on the nc pin co nfiguration. ic operation is not affected by leaving them open or by holding them fixed at particular levels. table 10.1 recommended circuit constant values symbol recommended value use remarks r0 50 to 1k ? ? r1 75 ? coaxial terminator r2 50k to 100k ? input amplifier feedback r3 1m ? oscillator amplifier feedback r4 150 to 330 ? oscillator amplifier current constraint r5 * pll loop filter tolerance: 5% c0 0.01 to 0.1 f ac coupling c1 1p to 33pf oscillator element l oad np0 special ceramic capacitor c2 * pll loop filter film capacitor c3 * pll loop filter ceramic capacitor c4 over 1 f power supply decoupling electrolytic capacitor c5 0.1 f power supply decoupling ceramic capacitor * : see section 8.3.1. dsp r5 c2 c3 2 3 4 5 6 7 8 9 10 18 17 16 15 19 20 ce cl do e / int a udio xin sdin datao lrck nc lpf LC89052TA-E nc 21 22 23 1 24 di pd error xout dgnd a gnd bck ckout dac a dc cpu r0 r1 r2 c0 c1 r4 r3 11 12 14 13 ugpi rxin a v dd dv dd c1 c4 c5 c4 c5
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